VeriSilicon SMIC 0.13um High-Density Standard Cell Library developed by VeriSilicon is optimized for Semiconductor Manufacturing International Corporation (SMIC) 0.13um Logic 1P8M Salicide 1.2/2.5V process, based on a nine track layout architecture.
The library supports most commonly used basic Boolean functions with multiple drive strengths. While satisfying the performance and power requirements, it was optimized for area efficiency.
SMIC 0.13um General Process, 1.2V/2.5V Standard Cell Library
Overview
Key Features
- VeriSilicon SMIC 0.13um High-Density Standard Cell Library uses metal 1 only within the cells and supports design with four, five, six, seven or eight layers of metal.
Deliverables
- Databook in electronic format
- Verilog models and Synopsys synthesis models
- Candence Silicon Ensenble Abstracts (LEF), Avanti! Apollo data, GDS II, LVS netlist
Technical Specifications
Foundry, Node
SMIC 0.13um
SMIC
Pre-Silicon:
130nm
EEPROM
,
130nm
G
,
130nm
LL
,
130nm
LV
Related IPs
- SMIC 0.13um High Vt Process, 1.2V/2.5V standard cell Library
- SMIC 0.13um Low Leakage UHD RVT_x005F_x000D_ Logic standard cell library, compatible with E-Flash and EEPROM process.
- SMIC 0.13um Low Leakage high density RVT_x005F_x000D_ Logic standard cell library.
- SMIC 0.13um Generic UHD RVT_x005F_x000D_ Logic standard cell library.
- GSMC 0.13um Low Power 7track Standard Cell Library,1.5v operating voltage
- GSMC 0.13um Low Power 9track Standard Cell Library,1.5v operating voltage