SLVS-MI/MIPI-DPHY Transmitter 4-Lane 2500Mbps

Overview

Key Features

• SLVS-MI / MIPI-DPHY v1-2 compliant
• Supporting for two kind Differential Output Signals
• 1) SLVS-MI (Maximum 2.5Gbps)
• 2) MIPI-DPHY (Maximum 2.5Gbps)
• Input Clock Frequency:
• (SLVS-MI 10bit SER) PCK_N= ~250MHz
• (MIPI-DPHY 8bit SER) PCK_N= ~313MHz
• Output Clock Frequency: ~1250MHz Output Data Rate: ~2.5Gbps
• Power Supply : 2.8V, 1.2V(PLL/BGR) 1.2V(PHY)
• Max TX Lane Number: 4-Lane Clock 1-port / Data 4-ports
• Data Input Path:
• 1) SLVS-MI (10bit Parallel)
• 2) MIPI DPHY (8bit Parallel)
• Include Power Down Mode
• Include Output clock's On/Off Mode
• Include Dp, Dm polarity Control
• Process: TPSCo 65nm BSB Triple well structure Layer: 7M/1L (1M~6M, 9M, L) 1.2V / 3.3V Transistor
• Various process porting support available (Please contact us.)
• Supporting Link-layer (Soft Macro): CD12821

Benefits

• We are IP design professional engineering company, so we can provide the high quality and good performance solution. Also we can provide not only single-interface PHY but also multi-interface PHY.
• We are making the PHY to meet customer specification by having our own IP data base resource. Our business is very flexibility IP license model, and then we have a lot of license to many sensor companies.
• Our products can contribute to your business.

Applications

• Camera Application
• Security Camera
• Mobile-Phone Camera
• DSC(Digital Still Camera)
• Medical Camera
• SLR
• 3D Camera
• Camcorder
• ISP(Image Signal Processer)

Deliverables

• Verilog Model (verilog / vcs)
• .db file / .lib(Option) file
• symbol / LVS netlist / Hspice netlist(Option)
• LEF, layer map file, layout technology file
• Layout Verification Report (DRC & LVS), Command file
• Datasheet (This file) /Application Note (Usage connection CIS)
• Packaging and Layout Guideline / PCB Guideline
• Static Delay Analysis (STA) Guideline
• Testing Guideline (Option)
• TX or RX Verilog Model and Test Vector(Option)
• CMOS Image Sensor Verilog Models(Option)
• Combo Link Layer IP(CD12821IP) and FPGA Board(Option)

Technical Specifications