Single Port SRAM Compiler IP, 4.0um2 bit cells, Synchronous high density, UMC 0.18um LL process
Overview
UMC 0.18um LL Logic process synchronous high density Single Port SRAM memory compiler.
Technical Specifications
Short description
Single Port SRAM Compiler IP, 4.0um2 bit cells, Synchronous high density, UMC 0.18um LL process
Vendor
Vendor Name
Foundry, Node
UMC 180nm LL
UMC
Pre-Silicon:
180nm
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