Serial protocol Interface Slave
Overview
The MSPIS IP implements a synchronous a single-chip SPI Slave IP capable of high speed serial data transfer with one SPI master. The MSPIS IP can be programmed to run either in standard SPI mode where bidirectional one byte transactions are implemented, or in extended SPI mode where frame transactions are implemented through 14-bits address and 16 or 32-bits data. The MSPIS IP controls all SPI-bus specific sequences, protocol and timing. This IP can be customized according to specific needs (application-specific requirement). Any other pre-designed functions can be integrated into the FPGA. FPGA density and I/O requirements can be defined according to customer specification.
Key Features
- Single-chip synchronous SPI Slave IP in FPGA
- Designed to be included in high-speed and high-performance applications
- Direct Connection to CPU register set
- High frequency rate
- Two run-time mode : Standard SPI mode and Extended SPI mode
- Synchronised on system clock
- Serial clock programmable with polarity and phase
- FPGA speed grade operating frequency dependant : system clock up to 220 MHz
- Available in VHDL source code format for ease of customization
- Can be customised by Logic Design Solutions
Deliverables
- VHDL Source code
- VHDL Test Bench for behavioural and gate level simulation.
- Data Sheet and Reference Guide
- User’s guide : Simulation, Synthesis and Place and Route procedures.
- Constraint File
- DO254 documentation available on request.
Technical Specifications
Availability
Now
Related IPs
- Serial Peripheral Interconnect Master & Slave Interface Controller
- Multi-Rate Serial Digital Interface (SDI) PHY Layer
- Tri-Rate Serial Digital Interface (SDI) Physical Layer (PHY)
- Single Wire Protocol (SWP) slave digital controller compliant with the ETSI 102.613 standard
- Single Wire Protocol (SWP) Slave Analog Front End (AFE) compliant with the ETSI 102.613 standard
- Serial Peripheral Interface – Master/Slave with Octal, Quad, Dual and Single SPI Bus support