IP Catalog > Interface IP > Interconnect IP > I2C IP > I2C Controller IP – Slave, SCL Clock, Parameterized FIFO, APB Bus. For low power requirements in I2C Slave Controller interface to CPU

I2C Controller IP – Slave, SCL Clock, Parameterized FIFO, APB Bus. For low power requirements in I2C Slave Controller interface to CPU

Overview

The DB-I2C-S-SCL-CLK-APB Controller IP Core interfaces an ARM, MIPS, PowerPC, ARC or other high-performance microprocessor via the AMBA 2.0 APB System Interconnect Fabric to an I2C Bus. The I2C is a two-wire bidirectional interface standard (SCL is Clock, SDA is Data) for transfer of bytes of information between two or more compliant I2C devices.

The DB-I2C-S-SCL-CLK-APB, in the I2C Slave Controller Core managing the I2C protocol & physical layer, contains no free running clock, while interfacing through dual clock FIFOs to the AMBA APB Bus, for a low power, low noise Microprocessor interface to the I2C Bus. The I2C Slave Controller Core runs off the external SCL clock while the APB side off the APB Clock.

The DB-I2C-S-SCL-CLK-APB Controller implements the Slave-Transmit and Slave Receive protocol according to the Philips I2C-Bus Specification, Version 2.1 as well as the updated NXP UM10204 Rev 7 – 1 Oct 2021 Specification.

The DB-I2C-S-SCL-CLK-APB is a member of the vendor  DB-I2C Controller IP Core family, which includes I2C Master/Slave, I2C Master-only, and I2C Slave-only configurations.

Figure 1 depicts the system view of the DB-I2C-S-SCL-CLK-APB Controller IP Core embedded within an ASIC, ASSP or FPGA device.

Key Features

  • Slave I2C Controller Modes:
    • Slave – Transmitter
    • Slave – Receiver
  • Supports four I2C bus speeds:
    • Hs-Mode (3.4+ Mb/s)
    • Fast Mode Plus (1 Mbit/s)
    • Fast Mode (400 Kb/s)
    • Standard Mode (100 Kb/s)
  • Low power, low noise applications requiring non-free running SCL Clock in the I2C protocol & physical layer logic processing and APB Clock only to interfaceto the Microprocessor.
  • Parameterized FIFO memory for off-loading the I2C transfers from the processor:
    • Targets embedded processors with higher performance algorithm requirements, by the I2C Controller independently controlling theTransmit or Receive of bytes of information buffered to and from a FIFO.
  • I2C compliant features:
    • Repeated Start, 7/10-bit addressing
  • Enhanced system-level features & integration capabilities:
    • CPU Interface via parameterized FIFO with support for APB / AHB / AXI / AXI-lite / Avalon interconnect fabrics
  • Enhanced system-level features & integration capabilities (OPTIONAL):
    • Direct interface to user Registers within ASIC / ASSP / FPGA device, for Master/Slave transfer across the I2C Bus
  • 5 sources of internal interrupts with masking control
  • Compliance with AMBA 2.0 and I2C specifications:
    • AMBA Specification (Rev 2.0), APB Bus
    • Philips/NXP – The I2C-Bus Specification, Version 2.1, January 2000 and UM10204 Rev 7 – 1 Oct 2021

Block Diagram

I2C Controller IP – Slave, SCL Clock, Parameterized FIFO, APB Bus. For low power requirements in I2C Slave Controller interface to CPU Block Diagram

Deliverables

  • The DB-I2C-S-SCL-CLK-APB is available in synthesizable RTL Verilog or a technology-specific netlist for FPGAs, along with Synopsys Design Constraints, a simulation test bench with expected results, datasheet, and user manual.

Technical Specifications

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