IP Catalog > Interface IP > Memory Interface IP > SATA IP > SATA PHY IP > Serial ATA1.5/3.0 Gbps PHY IP Core

Serial ATA1.5/3.0 Gbps PHY IP Core

Overview

The Mentor Graphics MSATA_PHYcore provides PHY layer functionality for a Serial ATA(SATA) interface operating at 3Gbps or 1.5Gbps. The MSATA_PHY core contains all the analog/mixed-signal components required to implement the industry standard SATA protocol within the physical layer and when combined with Mentor Graphics SATA Host or Device controller, the core provides a complete SATA hardware solution. The IP components include: transmitter drivers, receiver input buffers, impedance matching circuitry, amplitude and impedance calibration circuitry, parallel-to-serial and serial-to-parallel converters (serializer/deserializer) ,clock tuning & alignment mechanisms, OOB signal detection, clock speed & parallel bus width selection, test modes, and power management.

Key Features

  • Includes support for the following processes: -TSMC 130nm LVOD -SMIC 130nm G
  • Compliant to the Serial ATA specification
  • Selectable 1.5 Gbps or 3.0 Gbps high-speed serial data communication
  • Supports hot swapping
  • Configurable 40-, 20-, or 10-bit parallel controller interface
  • Analog portion front-end (AFE) resides inside IO pad ring occupying zero core area
  • All required Power Pads are contained within the core, all pins connected to external pads
  • Consumes less than 80mW (including termination power)

Deliverables

  • Verilog behavioral simulation model (NC-Verilog)
  • Integration and test guidelines
  • Application notes
  • DFE-Specific Deliverables:
  • Synthesizable Verilog RTLcode
  • Example synthesis scripts
  • Synthesis and static timing analysis reports
  • AFE-Specific Deliverables:
  • GDSII layout and layer map
  • Place and Route LIB & LEF views
  • LVS and DRC verification reports

Technical Specifications

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