SDRAM Assertion IP provides an efficient and smart way to verify the SDRAM designs quickly without a testbench. The SmartDV's SDRAM Assertion IP is fully compliant with standard SDRAM Specification.
SDRAM Assertion IP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env
SDRAM Assertion IP comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.