Fully Parameterized & Programmable Platform Level Interrupt Controller (PLIC) for RISC-V based Processor Systems supporting a user-defined number of interrupt sources and targets, and featuring a single AHB-Lite Slave interface
The core supports a programmable number of simultaneous pending interrupt requests per source and individual routing of those interrupt requests to each target, full interrupt prioritisation of each interrupt source and separate enables per target via a matrix of interrupt enable bits.
To reduce latency, the PLIC core presents all asserted interrupts to the target in priority order, queuing them so that a software interrupt handler can service all pending interrupts without the need to restore the interrupted context.
RISC-V Compliant Platform Level Interrupt Controller
Overview
Key Features
- AHB-Lite Interface with programmable address and data width
- User defined number of Interrupt Sources & Targets
- User defined priority level per Interrupt Source
- Interrupt masking per target via Priority Threshold support
- User defined Interrupt Pending queue depth per source
Block Diagram
Deliverables
- Full Source Code
- Testbenches
- Compilation Scripts
- Documentation
Technical Specifications
Availability
Fully released
Related IPs
- Intel 8259A Functional Equivalent Programmable Interrupt Controller
- Intel 8259A Functional Equivalent Programmable Interrupt Controller
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- ISO26262 ASIL-B/D Compliant 32-bit RISC-V Core