RapidIO
Overview
The Serial RapidIO® (SRIO) standard has been adopted by a significant portion of the wireless industry as a high-speed interconnect and is typically used between digital signal processors and between the control plane processors and memory. SRIO is also gaining acceptance as a backplane interconnect due to its adoption of widely used standards for the electrical characteristics of the physical medium attachment (PMA)—such as XAUI for the 3.125-Gbps data rate.
Key Features
- Feature rich
- Physical, transport, and logical layer separations (modular architecture)
- 1.25, 2.5, 3.125-Gbps lane rates -x1, x4 link widths
- Physical layer based on embedded transceivers or with parallel XGMII interface to external transceivers
- Easy to use
- MegaWizardTM Plug-In GUI allows easy manual optimization of parameters such as interface FIFO depths, address translation windows, and output differential voltage and pre-emphasis
- Easy configuration provides ways to reduce resource utilization to create smaller MegaCore® function variations depending on application needs
- SOPC Builder support
- Robust solution
- End-point intellectual property (IP) core, testbenches with proven interoperability with leading digital signal processor and switch vendors
- Compliant to RapidIO specification, Revision 1.3
Technical Specifications
Maturity
SOPC Builder Ready, I-Tested
Availability
Now