Vendor: Synopsys, Inc. Category: Mixed Signal Subsystem

Pre-verified Interface IP Subsystems reduce design risk and accelerate time-to-market

Customers are increasingly utilizing third-party standards-based IP in their designs, but face several challenges.

Overview

Customers are increasingly utilizing third-party standards-based IP in their designs, but face several challenges. With more IP and more complex interface protocols, the integration effort to incorporate all of the IP into an SoC can take much longer. Companies are spending as much on integration effort as they are on their IP while project schedules are getting shorter.
Synopsys Interface IP Subsystems, one part of the IP Accelerated initiative, reduce design risk and accelerate time-to-market. The Synopsys Interface IP Subsystems consist of pre-validated, fully integrated solutions that utilize Synopsys’ IP and tools for the specific SoC application. Synopsys Interface
IP Subsystems reduce the overall effort and cost of assembling and integrating IP into an SoC, allowing designers to focus their efforts on differentiating their product and speeding time-to-market.

Benefits

  • Accelerate interface IP subsystem development for complex protocols, such as DDR, PCIe®, USB, and Ethernet, as well as multiprotocol subsystems
  • Meet critical project schedules by using Synopsys IP protocol and SoC design experts to configure and customize the pre-designed subsystem to the unique SoC requirements
  • Minimize the subsystem integration effort through the use of pre-validated subsystem and verification tests focused on SoC integration
  • Reduce overall development costs while enabling designers to focus on their key competencies
  • Provide functionality and value over simple integration of a PHY and controller by including a common register interface between the PHY and controller, debug logic, and more

What’s Included?

  • Pre-configured, pre-validated Synopsys IP for controllers, PHYs and verification IP (VIP)
  • Supplemental subsystem logic for clock, reset, DMA, interrupts, and memory maps
  • Power management, debug, and testability logic
  • Complete subsystem verification environment that can also be leveraged for SoC verification:
  • Scoreboard, checkers and monitors for easy SoC debug
  • Comprehensive suite of tests that can be reused at SoC level

Specifications

Identity

Part Number
dwc_interface_ip_subsystems
Vendor
Synopsys, Inc.
Type
Silicon IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

Synopsys, Inc.
HQ: USA

Learn more about Mixed Signal Subsystem IP core

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Frequently asked questions about Mixed-Signal Subsystem IP cores

What is Pre-verified Interface IP Subsystems reduce design risk and accelerate time-to-market?

Pre-verified Interface IP Subsystems reduce design risk and accelerate time-to-market is a Mixed Signal Subsystem IP core from Synopsys, Inc. listed on Semi IP Hub.

How should engineers evaluate this Mixed Signal Subsystem?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Mixed Signal Subsystem IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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