PLL IP, Input: 20MHz - 200MHz, Output: 250MHz - 500MHz, UMC 0.13um HS/FSG process
Overview
The FXPLL130HC0H is a phase locked loop with an operating range of 250M~500MHz, UMC 0.13um HS/FSG Logic process.
Technical Specifications
Foundry, Node
UMC 130nm HS/FSG
UMC
Pre-Silicon:
130nm
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