PLL (Frequency Synthesizer) IP, Input: 20MHz - 200MHz, Output: 250MHz - 500MHz, UMC 0.13um HS/FSG process
Overview
Input 20M-200MHz, output 250M-500MHz (with duty ratio 40%~60%) and 125M~ 250MHz (with duty ratio 45%~ 55%), frequency synthesizable PLL, UMC 0.13um HS/FSG Logic process.
Technical Specifications
Foundry, Node
UMC 130nm HS/FSG
UMC
Pre-Silicon:
130nm
Related IPs
- PLL (Frequency Synthesizer) IP, Input: 20MHz - 200MHz, Output: 250MHz - 500MHz, UMC 0.11um HS/AE process
- PLL (Frequency Synthesizer) IP, Input: 20MHz - 200MHz, Output: 500MHz - 1GHz, UMC 0.11um HS/FSG process
- PLL (Frequency Synthesizer) IP, Input: 12MHz - 200MHz, Output: 250MHz - 500MHz, UMC 0.13um HS/FSG process
- PLL (Frequency Synthesizer) IP, Input: 20MHz - 200MHz, Output: 500MHz - 1GHz, UMC 0.13um HS/FSG process
- PLL IP, Input: 20MHz - 200MHz, Output: 250MHz - 500MHz, UMC 0.13um HS/FSG process
- PLL (Frequency Synthesizer) IP, Input: 20MHz - 200MHz, Output: 250MHz - 500MHz, UMC 0.13um HS/FSG process