PLL (Frequency Synthesizer) IP, Input: 66MHz - 100MHz, Output: 400MHz - 800MHz, UMC 90nm SP process
Overview
Input 66M-100MHz, output 400M-800MHz, frequency synthesizable PLL, UMC 90nm SP Logic process.
Technical Specifications
Foundry, Node
UMC 90nm SP
UMC
Pre-Silicon:
90nm
SP
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