PLL (Frequency Synthesizer) IP, Input: 33.33MHz - 100MHz, Output: 400MHz - 800MHz, UMC 55nm SP process
Overview
Input 33.33M-100MHz, output 400M-800MHz, frequency synthesizable PLL, UMC 55nm SP/RVT Low-K process.
Technical Specifications
Foundry, Node
UMC 55nm SP
UMC
Pre-Silicon:
55nm
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