PLL (Frequency Synthesizer) IP, Input: 5MHz - 100MHz, Output: 62.5MHz - 1000MHz, UMC 0.13um HS/FSG process
Overview
Input 5M-100MHz, output 62.5M-1000MHz, frequency synthesizable PLL, UMC 0.13um HS/FSG Logic process.
Technical Specifications
Short description
PLL (Frequency Synthesizer) IP, Input: 5MHz - 100MHz, Output: 62.5MHz - 1000MHz, UMC 0.13um HS/FSG process
Vendor
Vendor Name
Foundry, Node
UMC 130nm HS/FSG
UMC
Pre-Silicon:
130nm
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