PLL (Frequency Synthesizer) IP, Input: 25MHz - 50MHz, Output: 667MHz - 1300MHz, UMC 90nm SP process
Overview
Input 25M-50MHz, output 667M-1300MHz, frequency synthesizable PLL, UMC 90nm SP/RVT Low-K Logic process.
Technical Specifications
Short description
PLL (Frequency Synthesizer) IP, Input: 25MHz - 50MHz, Output: 667MHz - 1300MHz, UMC 90nm SP process
Vendor
Vendor Name
Foundry, Node
UMC 90nm SP
UMC
Pre-Silicon:
90nm
SP
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