PLL (All Digital, Spread Spectrum) IP, Input: 25MHz, Output: 5GHz, UMC 0.11um HS/AE process
Overview
5GHz SSCG with 25MHz reference clock, UMC 0.11um HS/AE (AL Advanced Enhancement) 2T Logic process.
Technical Specifications
Foundry, Node
UMC 110nm HS/AE
UMC
Pre-Silicon:
110nm
Related IPs
- PLL (All Digital, Spread Spectrum) IP, Input: 25MHz, Output: 5GHz, UMC 0.11um HS/AE process
- Temperature Sensor with Digital Output (High accuracy thermal sensing for reliability and optimisation), UMC 14FFC
- Spread Spectrum PLL on TSMC CLN40LP-ULP
- Single Port SRAM Compiler IP, UMC 65nm SP process
- Horizontal Down-scaler (Customized to two input resolutions and two output resolutions)**
- 2D Up-scaler (Customized to two input resolutions and two output resolutions)**