OTN Framer

Overview

Aliathon’s OTN Framer Core implements OTU, ODU and OPU layer functions and provides an integrated Reed-Solomon FEC codec in a flexible, resource-efficient FPGA based solution. Running at 166.62MHz or above, it is available for OTU1, OTU2 and OTU3 rates. OTU4 is under development.

Key Features

  • Conforms to G.709.
  • Generates the OTN frame structure and inserts framing overhead; detects and aligns to the OTN framing pattern.
  • Processes the OTN frame, OTUk Overhead, and Section Monitoring BIP. Processes ODUk Overhead, calculates and detects Path Monitoring BIP.
  • Supports synchronous payload mappings (eg: ATM, GFP), and asynchronous SONET/SDH mappings (accommodating positive/negative stuffing).
  • Detects LOS, LOF, MF-LOF, OTU AIS and ODU AIS, OCI and LCK defects.
  • Supports a contiguous payload interface: 16 bits wide for OTU1, 64 bits wide for OTU2, 256 bits wide for OTU3
  • Implements G.709 (255,239) OTN Reed Solomon encoding and low latency (27us) decoding. Flags all corrected bits, symbols and indicates uncorrectable codewords.
  • Full Overhead and Defect processing including:
    • LOS, LOF, MF-LOF.
    • OTUk Section Monitoring with TTI, BIP-8, BDI, BEI/BIAE. ODUk Path Monitoring with TTI, BIP-8, BDI, BEI, STAT (LCK, OCI, AIS). ODUk Tandem Connection Monitoring (TCM1-6) with TTI, BIP-8, BDI, BEI/ BIAE, STAT(LCK,OCI,AIS). OPUk PSI and PT.
    • Performance Monitoring counters (OTUk-BIP, ODUk-PM-BIP, ODUk-TCM-BIPs, BEI, corrected symbols, uncorrectable words).

Technical Specifications

Availability
now
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Semiconductor IP