PoS Framer

Overview

Aliathon’s Packet Over SONET/SDH (POS) Framer Core provides a flexible, resource-efficient, high-density programmable logic based solution for POS interfacing. Running at up to 155.52MHz, it is capable of PoS frame processing for data streams up to 10Gbps.

Key Features

  • Best-in-Class size and performance.
  • Multiple FPGA vendor support.
  • Available for the following SONET/SDH rates:
  • OC1/STM0, OC3/STM1, OC12/STM4, OC48/STM16, OC192/STM64
  • Processes data stream byte stuffing.
  • Generates flag characters for inter-frame gaps.
  • Inserts and detects CRC-16 and CRC-32.
  • Scrambles and descrambles the data stream using the X43+1 polynomial.
  • Indicates CRC, abort, alignment and framelength errors.
  • Ideal for FPGA-based systems processing POS over concatenated SONET/SDH.
  • Interfaces directly with SONET/SDH framer cores and bus interface cores (POS-PHY3).
  • Overhead and Defect processing including:
    • Frame Abort, CRC, Length Error Indicators.
    • Performance Monitoring Counters (CRC, Frame Abort).

Technical Specifications

Availability
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Semiconductor IP