Aliathon’s HDLC Framer Core provides a flexible, resource-efficient, high-density programmable logic based solution for HDLC interfacing. Running at over 155MHz, it is capable of generating and deframing thousands of HDLC channels.
HDLC Framer
Overview
Key Features
- Best-in-Class size and performance, supports many thousands of channels.
- Supports bit-synchronous and byte-synchronous HDLC.
- Generates/Accepts data for multiple independent TDM HDLC streams. Generates/Removes flag characters to delineate HDLC frames.
- Inserts/Removes HDLC bit or byte stuffing. Provides variable width data output.
- Calculates/Verifies and inserts CRC-16 and CRC-32.
- Scrambles/Descrambles the data stream using the X43+1 polynomial.
- Indicates CRC, abort, alignment and frame-length errors.
- Outputs/Accepts frame-aligned payload bytes.
- The line-side input/output data may dynamically range between 1 and 8 bits wide, allowing seamless interfacing to synchronous and asynchronous PDH framers.
- Configuration may be applied to each stream independently, and changed dynamically.
- Full Overhead and Defect processing per channel including:
- Frame Abort, CRC, Non Byte-Aligned, Length Error Indicators. Performance Monitoring Counters (CRC, Frame Abort).
Technical Specifications
Availability
now