Arasan Chip System’s NAND flash controller IP provides easy, reliable access to an off-chip NAND flash. It supports all modes of the Open NAND Flash Interface (ONFI) Specification, revision 5.0, release candidate 0.5, dated 1 March 2021. It is backwards compatible, supporting the Single Data Rate (asynchronous) mode, the double data rate moves NV-DDR, NV-DDR2, and NVDDR3, to include the latest NV-LPDDR4 recently introduced in the latest revision. All posted rates for these various modes are also supported, from the NV-DDR 33MHz mode at the low end all the way up to the newer 1,200MHz (2.4GT/s) I/O speeds.
The IP consists of two primary components: a host controller and two or more high speed PHY interface controllers. The host controller is controlled via an AXI slave port. A scatter/gather DMA provides a separate AXI master port, allowing for extended unattended reads or writes. The host controller supports either AXI3 or AXI4, and a user configurable data path width.
ONFI 5.0 Controller
Overview
Key Features
- ONFI v5.0 compliant + Up to 2.4GByte/s.
- All I/O modes implemented + SDR + NV-DDR + NV-DDR2/3 + NV-LPDDR4
- Wide hardware support + Four 8-bit data paths + 8 NAND targets each + Data bus inversion.
- Full PLL support + PLL within PHY + 10MHz SDR + 1.2GHz NV-LPDDR4 + Everything in between
- Configurable AXI ports — AXI3 or AXI4 — 32b–1024b bus widths
- AXI DMA master — Scatter / Gather — Parameterized width — Max Bus Throughput
- PHY BIST support
- Multiple host target processors — Maximizes throughput
Block Diagram
Technical Specifications
Availability
Now
Related IPs
- Supporting ONFI 6.0, 5.0, 4.2, 4.1, 4.0 and ONFI 3
- Supporting ONFI 5.0, 4.2, 4.1, 4.0 and ONFI 3 - TSMC 40nm 40G,LP,LP_eF,ULP,ULP_eF
- ONFI 5.0 PHY
- Supporting ONFI 5.0, 4.2, 4.1, 4.0 and ONFI 3
- Supporting ONFI 6.0, 5.0, 4.2, 4.1, 4.0 and ONFI 3
- UFS 4.0 Host Controller compatible with M-PHY 5.0 and UniPro 2.0