Near-threshold voltage and ultra-wide dynamic voltage and frequency scaling (UW-DVFS)

Overview

Minima Processor’s ultra-low power technology deploys patented Minima Dynamic Margining to minimize energy consumption of any digital logic. The Minima Dynamic Margining is a closed-loop, self-adapting IP that allows the digital sub-system to reach the near-threshold voltage while maintaining the capability to scale up when more computing power is needed. Minima Dynamic Margining allows the digital sub-system to always operate at the lowest possible energy for any given task, data or ambient condition.

Minima Dynamic Margining IP is foundry process and EDA tool flow agnostic. It targets processor cores like Arm Cortex-M series, Cadence Tensilica Hifi and Fusion families, NXP CoolFlux DSPs, etc. but it can be deployed to bigger digital blocks such as HW accelerators.

Key Features

Elimination of static margins
Operation at Near-Threshold Voltage (Minimum Energy Point)
Minima UWDVFS covers all operating points, scaling accurately to the minimum voltage needed by the application.

Benefits

Up to 15x energy improvement for digital logic
Ultra-wide Dynamic Voltage and Frequency scaling for flexibility
Foundry process agnostic
Standard EDA flow compatible

Applications

Always-on audio
Earbuds
TWS headset
Smart speakers
Hearing aid
Wireless Connectivity (LPWAN, BLE, WLAN, GPS)
IoT devices
Wearables
AR/VR

Deliverables

GDSII
Gate-level netlist
Standard Delay Format (SDF)
Library Exchange Format (LEF)
Liberty timing models (.lib)
Application note with integration and production test guidelines
DFT scan vectors
Minima IP driver and control software in ANSI-C

Technical Specifications

Foundry, Node

TSMC22, TSMC28, TSMC40, TSMC55, etc.

Maturity

Silicon proven

Availability

now

TSMC

Pre-Silicon: 22nm
Silicon Proven: 28nm HPCP

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