Multi-Link Multi-Protocol SerDes 10Gbps in TSMC 65GP

Overview

Key Features

• Configurable parallel data widths of 8 / 16 / 32 –bit
• Input reference 125MHz to support 2.5/5/10G data rates & 100MHz to support 2.5/5/8/16G data rates
• Tight control over termination resistor (~50 Ohm) with on chip calibration
• Tight skew control of 1UI between lanes of the PMA
• Multi-tap Tx Finite Impulse Response (FIR) equalizer with multi-level de-emphasis
• Continuous time linear equalizer (CTLE) with programmable settings providing up to 12dB gain peaking at Nyquist frequencies
• Programmable/automatic calibration of key circuits (pre-emphasis, eye-diagram monitoring / DFE tap calibration / offset calibration)
• CDR logic for better data alignment and locking
• Support for bifurcation and quadfurcation modes
• Multi-tap Rx DFE (decision feedback equalizer)
• Programmable internal/external

Benefits

• Single Supply: 1.0V±10%, Multi Standard with Programmable Pre-Emphasis and equalizer supporting data rate up to 16Gbps

Applications

• Enterprise routers
• Data storage
• Network communication
• Switches
• Repeaters and Re-timers

Deliverables

• GDS II Layouts
• LEF abstracts
• CDL netlists
• Liberty timings
• Verilog description
• A full datasheet
• An integration note

Technical Specifications