Dolphin Technology provides a complete NAND FLASH I/O library package. The package includes configurable IO's, power cells, fillers, spacers and analog cells. ESD and latch-up prevention structures are built-in into the library.
Multi Function IO interface (PCI/PCIX/DDR/LVDS/GPIO) - TSMC 40nm 40G,LP,LP_eF,ULP,ULP_eF
Overview
Key Features
- Supporting ONFI 4 and ONFI 3
- Pad design with 25um pitch
- Supports wirebond/CUP and flipchip packages
- Programmable metal stack options
- Single-ended IO and differential IO
- PVT Driver Compensation
- PVT RTT Compensation
- Built-in JTAG Logic for testability (Mentor or Synopsys compatible)
- Input/Output registers options
- Pulp-up/down options
- In-built ESD and Latchup Prevention circuits
- Power Clamp cells for ESD protection
- Compatible analog signal cells with ESD protection
Deliverables
- + Encrypted Verilog/SystemVerilog RTL, or post-synthesis netlist
- + Synthesis and STA scripts
- + User guide documents
- + SV/UVM Verification suite with BFM
Technical Specifications
Foundry, Node
TSMC 40nm
TSMC
Pre-Silicon:
40nm
G
,
40nm
LP
Related IPs
- Multi Rail LDO for SERDES on TSMC CLN2P
- DDR2/DDR3/DDR3L/LPDDR/LPDDR2/LPDDR3 6 in one combo IO with auto calibration - 40nm LL
- 5V I/O and ESD in TSMC 12nm FFC/FFC+
- Ultra-low leakage I/O Library in TSMC 22nm
- Wirebond I/O Library in TSMC 130nm
- SPI XIP Flash Memory Controller IP – Programmable IO & Execute-In-Place (XIP) via second AMBA Interface