IP Catalog > Interface IP > Interconnect IP > MIPI IP > MIPI Controller IP > MIPI DSI IP > MIPI DSI-2 with VESA DSC

MIPI DSI-2 with VESA DSC

Overview

Arasan’s Total IP Solution for MIPI Display Serial Interface (DSI-2) with VESA DSC IP provides both device and host functionality along with VESA DSC encoder and decoder functionalities that are defined in the latest MIPI DSI and VESA DSC specifications. This IP provides an end-to-end Total IP solution for the leading-edge displays enabling reduction in data transmission bandwidth for upto 4k or 8k displays with higher refresh rates and visually lossless compression. The DSI Controller provides a high-speed serial interface between an application processor and display and follows a rigorous verification methodology to ensure interoperability of our DSI digital controller with our D/C-PHY analog IP and VESA DSC components. Arasan’s DSI solutions are MIPI standards compliant and are designed to accelerate integration, lower risk, and accelerate time to market for developers of display applications. Arasan’s expertise is backed by our unique silicon-proven design discipline and product development process that ensures fast silicon success with our analog and digital IP.

Key Features

  • Fully compliant to MIPI DSI-2SM and VESA DSC standard
  • VESA DSC encoder/decoder is capable of decoding upto 4kvideo at 30fps in FPGA and 8K video at 30fps in ASIC applications
  • VESA DSC encoder/decoder is completely pipelined; can be stalled as necessary to properly manage input and output rates
  • VESA DSC encoder/decoder allows for migration from FPGA or FPGA prototype to ASIC with no functional changes to the core.
  • D-PHY 2.1 and CPHY 1.2 (Combo PHY)
  • Support for both Display Pixel Interface and Display Bus Interface
  • Encoder - Direct system interconnect interface like AXI and others for host control
  • Functionality ensured with comprehensive verification
  • Product quality is proven with silicon
  • Includes DSI controller and verification IP and Hardware Development Platform
  • AHB/APB Slave interface for programming control

Benefits

  • Fully compliant to MIPI and VESA standards
  • Small footprint
  • Code validated with HAL and 0-in-CDC
  • Functionality ensured with comprehensive verification
  • Product quality proven with silicon
  • Premier direct support from Arasan IP core designers

Block Diagram

MIPI DSI-2 with VESA DSC Block Diagram

Deliverables

  • Verilog HDL of the IP Core
  • Synthesis scripts
  • Verification environment
  • User guides for design and verification

Technical Specifications

Foundry, Node
TSMC & GF
Maturity
Silicon Proven
Availability
Now
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