VESA DSC Encoder

Overview

The VESA DSC and VDC-M IP cores deliver visually lossless video compression for mobile, AR/VR and automotive display applications.

The VESA DSC IP cores can compress any image to 8 bits per pixel (bpp), which results in a 3X compression ratio for a 24 bpp image or a 3.75X compression ratio for a 30 bpp image. The VDC-M cores use more sophisticated video encoding tools to achieve even higher compression factors for applications that require even more compression. VDC-M can reduce a 30 bpp uncompressed image to 6 bpp, and in some use cases, it can be visually lossless at a 6X compression ratio.

The VESA DSC and VDC-M IP cores can be combined with the MIPI DSI-2 Controller cores, and your choice of C/D-PHY, to form a complete display solution.

Key Features

VESA Display Stream Compression (DSC) 1.2b compliant
Supports all DSC 1.2b mandatory encoding mechanisms: MMAP, BP, MPP, and ICH
Output buffering compatible with transport stream over video interfaces
Configurable maximum display resolution
Configurable compressed bit rate, in increments of 1/16 bpp
8, 10, 12, 14, and 16 bits per video component
YCbCr and RGB video input format
4:4:4, 4:2:2, and 4:2:0 native coding
1 pixel / clock (Encoder) and 3 pixels / clock (Decoder) internal processing architecture in 4:4:4
2 pixel / clock (Encoder) and 6 pixels / clock (Decoder) internal processing architecture in 4:2:2 and 4:2:0
Parameterizable number of parallel slice encoder instances (1, 2, 4, or 8) to adapt to the capability of the technology and target display resolutions used
Multiple slices per line in each encoder instance supported
100% verification coverage based on UVM environment
Verified against the VESA DSC 1.2b C model using a comprehensive test image library
Backward compatible with DSC 1.1

VESA DSC Encoder

Overview

Key Features

Block Diagram

Deliverables

Technical Specifications

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