Innosilicon MIPI DSI-2 DSC RX IP implements the MIPI C/D-PHY as well as MIPI DSI-2 protocols and contains the DSC (Display Stream Compression) algorithm defined by VESA. The DSI-2 link protocol specification is a part of group of communication protocols defined by MIPI® Alliance, which is intended for mobile system chip to chip communications. The MIPI DSI-2 specification is specifically targeted for the display communications in image application processors.
Innosilicon MIPI DSI-2 DSC RX operates as a receiver of a DSI-2 link, which consists of a MIPI C/D combo PHY, a DSI-2 controller, and a DSC decoder.
? The MIPI C/D combo PHY is used for the data transmission from a DSI-2 compliant display module. In C/D combo PHY, data streams are organized as packets. Error information is generated for the application layer to do further operation.
? The DSI-2 controller works as a protocol layer between the application layer and physical layer, which aims to reconstruct the data streams from the C/D-PHY. Innosilicon DSI-2 controller implements all three layers defined by DSI-2 specification, including Pixel/Byte Packing, Low Level Protocol, and Lane Management.
? The DSC decoder algorithm is a visually lossless compression algorithm with a compression ratio of up to 3:1. The DSC algorithm enables low-cost hardware implementations of visually lossless video compression over display links.
MIPI DSI-2 DSC RX IP
Overview
Key Features
- Compliant with MIPI® Alliance Specification for Display Serial Interface (DSI-2) V1.0
- Compliant with MIPI® Alliance Specification for C-PHY V1.1
- Compliant with MIPI® Alliance Specification for D-PHY V1.2
- Compliant with MIPI® Alliance Specification for Display Command Set (DCS) V1.3
- Compliant with AMBA 3.0 APB Specification
- Compliant with VESA Display Stream Compression (DSC) Standard V1.1
- Data transfer rate ranging from 450Msps to 2.5Gsps per trio (C-PHY)
- Data transfer rate ranging from 400Mbps to 2.5Gbps per lane (D-PHY)
- Supports Pixel Interface and Packet Interface
- Supports data type: RGB/YCbCr (based on actual application scenarios)
- Asynchronous transfer at low power mode with a bit rate of 10 Mbps on both C-PHY and D-PHY
- Supports HS, LP, and ULPS modes
- Supports Skew-Calibration for D-PHY
- Bidirectional communication and escape mode support through data lane 0
- Automatic termination control for HS and LP modes
- Supports compression ratios of 3:1 and 2:1 for RGB
Deliverables
- Databook and detailed physical implementation guides for the complete PHY
- Library Exchange Format (LEF) file with pin size and locations
- Gate-level netlist and Standard Delay Format (SDF) Timing file
- Layout Versus Schematic (LVS) flattened netlist in spice format and report
- Encrypted Verilog Models
- GDSII database for foundry merge
- Module integration guidelines
- Silicon validation report (when available)
- Evaluation board (when available)
Technical Specifications
Foundry, Node
TSMC 12nm, SMIC 40/28nm
SMIC
In Production:
28nm
,
40nm
LL
Silicon Proven: 28nm , 40nm LL
Silicon Proven: 28nm , 40nm LL
TSMC
In Production:
12nm
Silicon Proven: 12nm
Silicon Proven: 12nm
Related IPs
- MIPI DSI-2 RX Controller
- MIPI D-PHY IP for TSMC (5nm, 6/7nm, 12/16nm, 22nm, 28nm, 40nm)
- MIPI C-PHY-D-PHY Combo PHY IP on TSMC 28nm HPC+
- MIPI CSI DSI C-PHY IP for TSMC (5nm, 6/7nm, 12/16nm, 22nm, 28nm, 40nm)
- MIPI D-PHY / C-PHY Combo IP for TSMC (5nm, 6/7nm, 12/16nm, 22nm, 28nm, 40nm)
- MIPI DSI-2 controllers with VESA DSC for high-speed serial interface between application processor and displays