The MXL-D-PHY-DSI-TX-T-28HPC+ is a high-frequency, low-power, low-cost, source-synchronous, physical Layer supporting the MIPI Alliance Specification for D-PHY v2.5.
The PHY can be configured as a MIPI Master supporting display interface DSI/DSI-2. The PHY supports mobile, IoT, virtual reality, and automotive applications.
MIPI D-PHY DSI TX (Transmitter) in TSMC 28nm
Overview
Key Features
- Supports MIPI Alliance Specification for D-PHY Version 2.5
- Consists of 1 Clock lane and 4 Data lanes
- Supports both low-power mode and high-speed mode with integrated SERDES
- 80 Mbps to 1.5 Gbps data rate per lane without skew calibration in D-PHY mode
- 2.5 Gbps data rate per lane with skew calibration in high-speed D-PHY mode
- 10 Mbps data rate in low-power mode
- Low power dissipation
- Testability support
- Calibrator for resistance termination
Benefits
- This MIPI D-PHY IP supports MIPI DSI, MIPI DSI-2, as well as MIPI CSI-2
Block Diagram
Applications
- Mobile
- Display
- IoT
- VR/AR/MR
- Consumer electronics
- Automotive
Deliverables
- Specifications
- GDSII
- LVS netlist
- LEF file
- IBIS Model
- Verilog Model
- Timing Model
- Integration Guidelines
- RTL
- Documentation
- One year support
Technical Specifications
Foundry, Node
TSMC, CRN28HT
Maturity
Available Upon Request
Availability
Now