MIPI D-PHY DSI RX (Receiver) in UMC 40HV

Overview

The MXL-DPHY-DSI-RX is a high-frequency low-power, low-cost, source-synchronous, Physical Layer supporting the MIPI Alliance Specification for D-PHY v1.1.
The IP is configured as a MIPI Slave optimized for DSI (Display Serial Interface) applications.
The High-Speed signals have a low voltage swing, while Low-Power signals have large swing. High-Speed functions are used for High-Speed data traffic while low power functions are mostly used for control.

Key Features

  • Consists of 1 Clock lane and up to 4 Data lanes
  • Supports MIPI® Alliance Specification for D-PHY Version 1.1
  • Supports both high speed and low-power modes
  • 80 Mbps to 1.5 Gbps data rate in high speed mode
  • 10 Mbps data rate in low-power mode
  • High Speed Deserializers included
  • Low power dissipation
  • Testability support
  • Optional resistance termination calibrator

Benefits

  • Area and performance optimized for DSI RX, silicon proven in UMC 40HV

Block Diagram

MIPI D-PHY DSI RX (Receiver) in UMC 40HV Block Diagram

Applications

  • Mobile
  • Displays
  • IoT
  • VR/AR/MR
  • Consumer electronics
  • Automotive

Deliverables

  • Specifications
  • GDSII
  • LVS netlist
  • LEF file
  • IBIS Model
  • Verilog Model
  • Timing Model
  • Integration Guidelines
  • RTL
  • Documentation
  • One year support

Technical Specifications

Foundry, Node
UMC, 40HV
Maturity
Silicon Proven
Availability
Now
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Semiconductor IP