LDPC Encoder/Decoder (LDPC)

Overview

Key Features

• LDPC IP scalability
• Supporting a wide range of data-rates
• 50MB/s to 4.0GB/s for a single LDPC instance
• Scalable platform provides the basis for customer specific custom-LDPC cores
• Each LDPC IP is optimized for
• Codeword size, supports wide range of codewords
• Maximum amount of supported parity
• High degree of parallelism for high data-rate applications
• Different Memory access options
• Platform specific options (eASIC, FPGA, 40nm ASIC, 28nm ASIC)
• All LDPC IP Cores share the following features
• Simultaneous support for different amounts of parity
• Simultaneous support for several LDPC codes
• On-the-fly switching from one LDPC code to another
• Low area and power

Benefits

• Patented technology delivers the industry’s highest reliability, highest performance, and lowest power for next-generation flash controllers
• Dramatic increases in P/E cycles significantly extends the life of flash memory
• Addresses the reliability challenges of MLC, TLC and 3D Flash at 1y and 1z nm geometries
• Access to flash manufacturer’s test mode commands to enable the generation of soft information for optimal reliability performance

Block Diagram

Applications

• Flash Storage

Deliverables

• Product Package
• Source Code for LDPC Compiler - Parametrizeable Verilog, Perl
• Source Code for LDPC Matrix Generation Software
• FPGA reference design platform with Matlab interface
• Documentation
• IP user guide
• Synthesis Guide

Technical Specifications