The Integer PLLs generate a stable clock from low frequency reference clock.
Operate on a core power supply. Have mass production results at each technology node.
Integer PLL (40nm - 110nm)
Overview
Key Features
- Has general Integer PLL functions.
- The power supply uses only core voltage.
- Spread Spectrum Tracking.
- Includes Unlock Detector (TSMC 40nm (CLN40ULP), 55nm(CLN55LP), UMC 55nm(LP) only ).
Applications
- General Purpose
Deliverables
- GDSII
- CDL netlist
- Verilog model
- Synopsys synthesis model
- LEF
- User Guidelines
Technical Specifications
Foundry, Node
TSMC 40nm (CLN40LP/CLN40ULP), 55nm(CLN55LP), 110nm(CLN110G), UMC 55nm(LP)
Maturity
In Production
TSMC
In Production:
40nm
LP
,
55nm
LP
,
110nm
G
Silicon Proven: 40nm LP , 55nm LP , 110nm G
Silicon Proven: 40nm LP , 55nm LP , 110nm G
UMC
In Production:
55nm
Silicon Proven: 55nm
Silicon Proven: 55nm
Related IPs
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- NVM OTP in TSMC (180nm, 152nm, 130nm, 110nm, 90nm, 65nm, 55nm, 40nm, 28nm, 22nm, 16nm, 12nm, N7, N6, N5, N4P)
- NVM OTP in UMC (180nm, 153nm, 110nm, 90nm, 80nm, 55nm, 40nm, 28nm, 22nm)
- Core Powered Wide Range Programmable Integer PLL on TSMC CLN2P