This is an I3C Master and Slave Dual Controller IP which can manage Master as well as Slave and encounters the MIPI I3C standard. I3C Dual controller is completely designed and has the ability to provide an I3C connection for any device. I3C master and the Slave both arranged by this IP. It is used for configured in a number of different ways to meet very low gate count and power requirements.
I3C Master and Slave Dual Controller IP
Overview
Key Features
- Amenable for a contemporary version of the MIPI I3C specification
- Attribute of I3C
- I2CPatrimony
- Hot-join Dynamic Address Assignment
- Status I2C address support
- I2C pads reinforcement with 50ns glitch filter
- Interrupts of InBand
- In Mode 0 Asynchronous time stamping
- Ancillary CCC’s
- HDR-DDR High-speed mode
- Compatible SOC Side Interface Options
- Low Power
- AMBA AXI 4.0
- AMBA AHB 2.0
Applications
- Mixed Signal Digital
- Small Controller,Temperature,Pressure,NFC,Industrial,Personal Health Monitors,Acceleration Monitors Sensors
- SPI Devices
- I3C Connected Devices
- Smart Lighting Controls
- Legacy 12C Devices
Deliverables
- Verilog RTL source code
- System Verilog test bench with test suites
- System Verilog I3C Master and slave bus functional model
- System Verilog I3C Bus Monitor
- Provided as source code, no additional licenses required
- Master controller (binary) for developing/testing FPGA prototypes
- Documentation including User's Guide and Integration Guide
- Technology-independent synthesis constraints