High Speed Low Power JPEG Codec IP Core
High Speed Low Power JPEG Codec IP Core
Overview
Key Features
- ISO/IEC 10918-1/2(JPEG) Compliant
- Base Line Support (Progressive is not supported)
- Encode Format
- Y:CB:CR = 4:2:2, 4:1:1
- Automatic Header Handling
- Generate/Read a variety of JPEG header information (Marker Code, Parameter) automatically.
- Quantization Table
- Implement 3 quantization tables for Y/Cb/Cr respectively as default.
- Possible to program tables from external CPU.
- Encode/Decode process performance
- 92Mbyte/sec (@100MHz CLK) Same performance for both ENC/DEC
- (DCT/IDCT, Q/IQ to be processed at 1-pixel/cycle)
- Example of YUV420
- 640×480×200fps
- 1280×1024×70fps
Block Diagram
Deliverables
- Verilog RTL
- Synthesis Environment
- Test Environment
- Datasheet & Documents
Technical Specifications
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