High speed low latency AES-GCM pipeline, 100Gbps

Overview

Key Features

• Silicon-proven implementation
• Fast and easy to integrate into SoCs
• Flexible layered design
• World-class technical support

Benefits

• The AES-IP-61mc AES-CTR core is able to process 1 data block of 256-bit size per clock cycle when there are less than or equal to 5 key/IV switches in 15 clock cycles. Two clock cycles are required to load one key/IV pair:
  • 256-bit data-path using 28 AES cores with 256-bit key size
  • Symmetric AES-CTR block cipher encrypt and decrypt operations
  • 10-channel encoding with 2 pairs of keys and IV per channel
  • Key switching without performance drop (or hit)
  • Key scheduling in hardware
  • Non-encrypted data bypass per block
  • Fake encryption test mode
  • Wide bus interface, 128 bit for data, 256 bit for keys
  • Fully synchronous design
• The AES-IP-61mg, GHASH core is able to process one data block of 256-bit size per clock cycle and the key switch between data blocks does not require any additional clock cycles as long as there are at least six data blocks processed sequentially with the same key and the minimum frame size is eight data blocks. If a frame is being finalized and there are less than seven data blocks processed sequentially, the AES-GMAC core needs one extra clock to finalize the operation:
  • 256-bit data-path
  • AES-GMAC (using GHASH) with 256-bit key size
  • Hash key (H) calculation
  • 10-channel encoding with 2 pairs of keys and IV per channel
  • Key switching without performance drop (or hit) for both encryption and description
  • 64-bit and 128-bit authentication tags over a statically configurable number of 128-bit blocks
  • Wide bus interface, 128 bit for data, 256 bit for keys
  • Fake authentication test mode
  • Memory interface for storing keys, IV, key derivatives and intermediate state

Block Diagram

Deliverables

• Documentation
  • Hardware Reference and Programmer Manual
  • Integration Manual
  • Verification Specification
• Synthesizable Verilog RTL source code
• Self-checking RTL test bench, including test vectors and expected result vectors
• Simulation scripts
• Configurations:
  • EIP-61 v1
    • AES-GCM
    • 199-385K gates
    • 128 bits/clk
    • up to 1 Ghz
  • EIP-61 v2
    • AES-CTR/AES-GMAC
    • 130k-375K gates
    • 256 bits/clk
    • up to 800 Mhz

Technical Specifications