High Performance 64-bit RISC-V Multi-Core Application Processor
Overview
The U7 Series features SiFive’s highest-performance RISC-V Linux-capable application processor. The U7 core has a superscalar 8-stage pipeline with support for virtual memory, enabling the most demanding 64-bit RISC-V applications such as Edge Compute, Big-Data Analytics and 5G Base Stations.
Key Features
- U7 allows for instantiation of up to 9 U7 and/or S5 cores as well as a configurable Level 2 Cache
- U7 Core Architectural Features
- RV64GCV capable core with Sv39 Virtual Memory Support
- Dual Issue, in-order 8 stage Harvard Pipeline
- Optional SECDED ECC support on Level 1 and Level 2 memories
- Performance and Area
- DMIPS – 2.5 DMIPS/MHz
- Coremark – 5.1 Coremarks/MHz
- SPEC – U54 + 40%
- Core Area is ~30% larger than equivalent U5 Core
- Functional Safety and Security and Real Time features
- SECDED ECC on all L1 and L2 memories
- User Mode Interrupts for compartmentalization
- Programmatically clear and/or disable dynamic branch prediction for deterministic execution and enhanced security
- Configurable EXX minion cores can provide a variety uses
- System boot and monitor, Sensor Hub/Fusion, Security Co-Processor
Applications
- General purpose embedded
- Industrial
- IoT
- High-performance real-time embedded
- Automotive
Deliverables
- RTL Evaluation
- Test Bench RTL
- Software Development Kit
- FPGA Bitstream
- Documentation
Technical Specifications
Maturity
Now
Related IPs
- High-performance 64-bit RISC-V architecture multi-core processor with AI vector acceleration engine
- 64-bit RISC-V Multi-Core Linux-Capable processor
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- High performance 32-bit RISC-V Processor
- 32-bit RISC-V High Performance Microcontroller Class Processor
- 32b/64b RISC-V 5-stage, scalar, in-order, Application Processor. Linux and multi-core capable. Maps upto ARM A-35. Optimal PPA.