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GDDR4 Memory Model

Overview

GDDR4 Memory Model provides an smart way to verify the GDDR4 component of a SOC or a ASIC. The SmartDV's GDDR4 memory model is fully compliant with standard GDDR4 Specification and provides the following features. Better than Denali Memory Models.

GDDR4 Memory Model is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env

GDDR4 Memory Model comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.

Key Features

  • Supports GDDR4 memory devices from all leading vendors.
  • Supports 100% of GDDR4 protocol standard GDDR4Spec_rev_04.
  • Supports all the GDDR4 commands as per the specs.
  • Quickly validates the implementation of the GDDR4 standard GDDR4Spec_rev_04.
  • Supports for programmable clock frequency of operation.
  • Supports for all types of timing and protocol violation detection.
  • Supports for all mode registers programming.
  • Supports for Double data rate architecture.
  • Supports for Single ended READ strobe (RDQS) per byte.
  • Supports for Single ended WRITE strobe (WDQS) per byte.
  • Supports for Quad or eight internal banks for concurrent operation.
  • Checks for following
    • Check-points include power on, Initialization and power off rules,
    • State based rules, Active Command rules,
    • Read/Write Command rules etc.
    • All timing violations.
  • Supports for Programmable Burst Length 8.
  • Supports for Data mask (DM) for masking WRITE data.
  • Supports for Multiplexed addressing.
  • Supports for Auto Precharge option for each burst access.
  • Supports for Auto Refresh and Self Refresh Modes.
  • Supports for On‐die termination (ODT).
  • Supports for Programmable offset for both driver and termination.
  • Supports for Parity and Boundary Scan.
  • Supports for input clock stop and frequency change.
  • Notifies the test bench of significant events such as transactions, warnings, timing and protocol violations.
  • Protocol checker fully compliant with GDDR4Spec_rev_04.
  • Constantly monitors GDDR4 behavior during simulation.
  • Built in functional coverage analysis.
  • Supports Callbacks, so that user can access the data observed by monitor.

Benefits

  • Faster testbench development and more complete verification of GDDR4 designs.
  • Easy to use command interface simplifies monitor control and configuration.
  • Simplifies results analysis.
  • Runs in every major simulation environment.

Block Diagram

GDDR4 Memory Model Block Diagram

Deliverables

  • Complete regression suite containing all the GDDR4 testcases.
  • Examples showing how to connect and usage of Model.
  • Detailed documentation of all class, task and function's used in verification env.
  • Documentation also contains User's Guide and Release notes.

Technical Specifications

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