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GDDR6 Memory Model

Overview

GDDR6 Memory Model provides an smart way to verify the GDDR6 component of a SOC or a ASIC. The SmartDV's GDDR6 memory model is fully compliant with standard GDDR6 Specification and provides the following features. Better than Denali Memory Models.

GDDR6 Memory Model is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env

GDDR6 Memory Model comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.

Key Features

  • Supports GDDR6 memory devices from all leading vendors.
  • Supports 100% of GDDR6 protocol standard JESD250, JESD250A, JESD250B and JESD250C specification with version 3.12.
  • Supports all the GDDR6 commands as per the specs.
  • Supports 2 separate independent channels with point-to-point interface for data, address and command.
  • Supports Double Data Rate (DDR) or Quad Data Rate (QDR) data.
  • Supports Pseudo channel mode operation.
  • Supports up to 32GB device density.
  • Supports X8 and X16 Mode.
  • Supports RDQS Mode.
  • Supports DQ preamble.
  • Supports Bank group features.
  • Supports Programmable READ/WRITE latency.
  • Supports Bank grouping and 16 internal banks per channel.
  • Supports Data bus inversion (DBI) & Command Address bus inversion (CABI).
  • Supports Read/Write data transmission integrity secured by cyclic redundancy check.
  • Supports Input/output PLL/DLL on/off mode.
  • Supports READ/WRITE EDC on/off mode.
  • Supports WRITE Data mask function (single/double byte mask).
  • Supports Programmable EDC hold pattern for CDR.
  • Supports Programmable CRC READ/WRITE latency.
  • Supports Low Power modes.
  • Supports Refresh Management(RFM).
  • Supports Auto refresh & self-refresh modes.
  • Supports On-die termination operation.
  • Supports Vendor ID1 and ID2 for identification.
  • Supports COMMAND ADDRESS, WCK2CK,READ/WRITE Training mode’s.
  • Supports IEEE.1149.1 boundary scan operation.
  • Checks for following
    • Check-points include power on, Initialization and power off rules,
    • State based rules, Active Command rules,
    • Read/Write Command rules etc.
    • All timing violations.
  • Supports callbacks for user to get command data on bus.
  • Supports all mode registers programming.
  • Supports for power down features.
  • Supports for input clock stop and frequency change.
  • Quickly validates the implementation of the standard GDDR6 protocol JESD250, JESD250A, JESD250B and JESD250C specification with version 3.12.
  • Bus-accurate timing for min, max and typical values.
  • Constantly monitors GDDR6 behavior during simulation.
  • Protocol checker fully compliant with GDDR6 standard JESD250, JESD250A, JESD250B and JESD250C specification with version 3.12.
  • Notifies the test bench of significant events such as transactions, warnings, timing and protocol violations.
  • Built in functional coverage analysis.
  • Supports Callbacks, so that user can access the data observed by monitor.

Benefits

  • Faster testbench development and more complete verification of GDDR6 designs.
  • Easy to use command interface simplifies monitor control and configuration.
  • Simplifies results analysis.
  • Runs in every major simulation environment.

Block Diagram

GDDR6 Memory Model Block Diagram

Deliverables

  • Complete regression suite containing all the GDDR6 testcases.
  • Examples showing how to connect and usage of Model.
  • Detailed documentation of all class, task and function's used in verification env.
  • Documentation also contains User's Guide and Release notes.

Technical Specifications

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