Universal Memory Controller for SDRAM, SyncFlash, NorFlash and Static Memory

Key Features

• SDRAM Interface
• Glueless connection to all JEDEC-compliant SDRAM
• Shared memory address and data buses between SDRAM and Static memories
• Supports up to 13 SDRAM address bits
• SDR-SDRAM and SyncFlash memory data width that can be configured to 8, 16 or 32 bit
• Programmable parameters: 8 - 12 bit column address; 10 - 13 bit row address; CAS latency: 1-4 cycles ; burst or single write; read pipeline: adds an extra latency cycle for external synchronization; actual timing (TRCD , TRP , TDAL , TRC , TWR)
• Supports 2 and 4 banks
• Supports AutoRefresh and Powerdown
• Flash Interface
• Glueless connection of SyncFlash and NorFlash
• Data width that can be configured to 8, 16 or 32 bit
• Implementation of the Software Command Sequence
• Implementation of the Hardware Command Sequence for SyncFlash
• Supports Powerdown
• Static Memory Interface
• support of SRAM and ROM type (static) memories
• AMBA AHB Interface Features
• AMBA V2.0 AHB bus-compatible
• Supports the following AMBA features: nonsequential, sequential, idle and busy bus cycles; single, INCR, INCR4, INCR8, INCR16, WRAP4, WRAP8, WRAP16
• Supports AHB data widths of 32 bits
• Supports AHB address width of 32 bits
• Supports narrow access on wide AMBA bus
• Does not generate split and retry responses on the AMBA bus
• Up to 200MHz clock frequency

Deliverables

• Verilog RTL
• Testbench
• Synthesis Script
• Manual

Technical Specifications