Foundation IP (Memory Compliers & Standard Cell Libraries)

Overview

Key Features

• Memory Compilers
• Low Leakage with retention (light and deep sleep)
• Power Gating with retention and without retention
• Dual Rail (SRAM Periphery at lower Voltage)
• Combinations of above low power options
• Generate larger instances(up to 2Mbits)
• BIST solution optimized to our memories
• Standard Cell Libraries
• High Performance Library Variant
• Low Power Library Variant

Benefits

• Zixin provides a broad portfolio of high-quality, silicon-proven foundation IP, including memory compilers, logic libraries, and general-purpose I/O (GPIO), enabling system-on-chip (SoC) designers to lower integration risk and speed time-to-market
• Each one has been optimized for speed, routability, power and density, in order to maximize performance and wafer yield while lowering overall SoC cost
• Wide process coverage from 90/80/65/55/40 to 7/6, 7+/5/5+ nm

Technical Specifications