Enhanced UART with FIFOs & IrDA Support

Overview

The M16x50 is an extension of the Inventra M16550S UART with FIFOs, with enhancements that emulate features found in similar discrete devices with a range of part numbers. Some of the enhancements are enabled by software and are always present in the design: some - such as maximum FIFO size - are configurable and are selected on compilation. Like the M16550S, the M16x50 offers programmable word length (from five to eight bits), together with an optional parity bit and 1, 1½ or 2 stop bits.If enabled, the parity can be odd, even or forced to a defined state. Also like the M16550S, the M16x50 includes a 16-bit programmable baud rate generator, an 8-bit scratch register and two DMA handshake lines, TXRDY and RXRDY, which are used to indicate when the FIFOs are ready to transfer data to the CPU. Further, the DMA handshake lines may be configured either to support single-byte transfers (DMA Mode 0) or multiple-byte transfers (DMA Mode 1). The M16x50 also includes eight modem control lines and a diagnostic loop-back mode. Interrupts can be generated for a range of TX Buffer/FIFO, RX Buffer/FIFO, Modem Status and Line Status conditions.

Key Features

  • Software compatible with 16C450- and 16550A-compatible UARTs
  • Hardware & Software Flow Control
  • IrDA Modulation/Demodulation
  • Transmit FIFO Threshold
  • Configurable FIFO Depth
  • CTS and RTS Interrupts
  • Programmable word length, stop bits and parity
  • Programmable baud rate generator
  • Diagnostic loop-back mode
  • Fully synthesizable
  • Scan test ready

Deliverables

  • Verilog source code
  • VHDL source code
  • Synthesis script for Design Compiler
  • Verilog & VHDL testbenches
  • Reference technology netlist
  • Product Specification & User Guide

Technical Specifications

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