DO-254 LMB BRAM Interface Controller 1.00a
Overview
The interface between the LMB and the BRAM block peripheral. A BRAM memory subsystem consists of the controller along with the actual BRAM components that are included in the BRAM block peripheral. Almost certainly needed for any MB system.
Key Features
- LMB v1.0 bus interfaces with byte enable support
- Used in conjunction with BRAM block peripheral to provide fast BRAM memory solution for MicroBlaze™ ILMB and DLMB ports
- Supports byte, half-word, and word transfers
Benefits
- Mature source IP has been re-engineered for full DAL-A compliance for airworthiness and design assurance for safety-critical programs, supporting and simplifying the compliance effort at the FPGA level.
Deliverables
- Encrypted source along with a complete certification data package (CDP) including all artifacts required for chip-level compliance.
Technical Specifications
Availability
March 2014
Related IPs
- DO-254 Local Memory Bus (LMB) 1.00a
- DO-254 Tri-Mode Ethernet Media Access Controller (TEMAC) 1.00a
- LMB BRAM Interface Controller
- ISO/IEC 7816-3 digital controller for interface device compliant with ETSI TS 102 221 and EMV 2000 standards
- DO-254 AXI4-Lite IPIF 1.00a
- DO-254 AXI 7-Series DDRx (Limited) 1.00a