Maps AXI4 transactions coming from the MicroBlaze™ to the User Interface Block providing an industry-standard bus protocol interface to the memory controller. It enables the MicroBlaze™ to use external SDRAMs through the AXI4 interface, thereby increasing its versatility. Basically it is a memory controller for 7-series devices (higher speed, more complex), takes care of refreshing memories, etc.
DO-254 AXI 7-Series DDRx (Limited) 1.00a
Overview
Key Features
- DDR3 SDRAM Features
- Component support for interface widths up to 64 bits
- Single rank UDIMM and SODIMM support
- DDR3 (1.5 V) and DDR3L (1.35 V)
- 1, 2, and 4 Gb density device support
- 8-bank support
- x8 and x16 device support
- 8:1 DQ:DQS ratio support
- Configurable data bus widths (multiples of 8, up to 64 bits)
- 8-word burst support
- Support for 5 to 11 cycles of column-address strobe (CAS) latency (CL)
- On-die termination (ODT) support
- Support for 5 to 8 cycles of CAS write latency
- Write leveling support for DDR3 (fly-by routing topology required for DDR3 component designs)
- JEDEC-compliant DDR3 initialization support
- Source code written in Verilog
- 4:1 and 2:1 memory to FPGA logic interface clock ratio
- Internal VREF support
- Multicontroller support for up to eight controllers
- Two controller request processing modes:
- Normal: Reorder requests to optimize system throughput and latency
- Strict: Memory requests are processed in the order received
- DDR2 SDRAM Features
- Component support for interface widths up to 64 bits
- Single rank UDIMM and SODIMM
- 1 and 2 Gb density device support (additional densities supported in the MIG tool using the Create Custom Part feature)
- 4- and 8-bank support
- x8 and x16 device support
- 8:1 DQ:DQS ratio support
- Configurable data bus widths (multiples of 8, up to 64 bits)
- 8-word burst support
- Support for 4 to 5 cycles of column address strobe (CAS) latency
- On-die termination (ODT) support
- JEDEC-compliant DDR2 initialization support
- Source code written in Verilog
- 4:2 and 2:1 memory to FPGA logic interface clock ratio
- Internal VREF support
- Two controller request processing modes:
- Normal: Reorder requests to optimize system throughput and latency
- Strict: Memory requests are processed in the order received
Benefits
- Mature source IP has been re-engineered for full DAL-A compliance for airworthiness and design assurance for safety-critical programs, supporting and simplifying the compliance effort at the FPGA level.
Deliverables
- Encrypted source along with a complete certification data package (CDP) including all artifacts required for chip-level compliance.
Technical Specifications
Availability
March 2014