DLL IP, Input: 100MHz - 400MHz, Output: 100MHz - 400MHz, UMC 0.11um HS/FSG process
Overview
Input 100M~400MHz, Output 100M~400MHz DLL-based cell that generates two-channel DQS with 25% timing delay, UMC 0.11um HS/RVT Logic process.
Technical Specifications
Foundry, Node
UMC 110nm HS/FSG
UMC
Pre-Silicon:
110nm
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