DDR DLL IP, Input: 100MHz - 400MHz, Output: 100MHz - 400MHz, UMC 65nm SP process
Overview
Input 100-400MHz, output 100-400MHz, DDR2 DLL, UMC 65nm SP/RVT Low-K Logic process.
Technical Specifications
Foundry, Node
UMC 65nm SP
UMC
Pre-Silicon:
65nm
SP
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