DLL-based cell that generates 32 phase delay for SDIO; Frequency range: 52MHz~208MHz; UMC 28nm HPC Logic Process
Overview
DLL-based cell that generates 32 phase delay for SDIO; Frequency range: 52MHz~208MHz; UMC 28nm HPC Logic Process
Technical Specifications
Short description
DLL-based cell that generates 32 phase delay for SDIO; Frequency range: 52MHz~208MHz; UMC 28nm HPC Logic Process
Vendor
Vendor Name
Foundry, Node
UMC 28nm
UMC
Pre-Silicon:
28nm
HLP
,
28nm
HPC
,
28nm
HPM
,
28nm
LP
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