DLL (All Digital) IP, Input: 300MHz - 600MHz, Input: 300MHz - 600MHz, UMC 40nm LP process
Overview
An ADDLL operate at 300MHz~600MHz.Output 0-180 degree Phase adjustment range.Delay adjustment resolution <= 1% of reference clockUMC 40nm LP/RVT Logic process.
Technical Specifications
Foundry, Node
UMC 40nm LP
UMC
Pre-Silicon:
40nm
LP
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