DDR3 SDRAM Controller for UniPHY
Benefits
- SOPC Builder Ready: No
- Qsys Compliant: No
Technical Specifications
Related IPs
- DDR3 SDRAM Controller
- DDR3 SDRAM Controller supporting Altmemphy
- DDR2 SDRAM Controller for UniPHY
- I2C Controller IP – Slave, SCL Clock only, principally for configuring registers in mixed-signal ICs with low noise or low power requirements
- I2C Controller IP – Slave, SCL Clock, Parameterized FIFO, APB Bus. For low power requirements in I2C Slave Controller interface to CPU
- DDR3 SDRAM Controller