DDR3 / DDR4 Combo I/O Pad Set
Overview
The DDR3 / DDR4 library includes the combo driver/receiver cells with embedded power cells, the driver impedance calibration cell, and a full complement of support cells for both single-ended and differential signaling for DDR3 and DDR4 applications. Also included is a full complement of power, corner and spacer cells to assemble a complete pad ring by abutment. An included rail splitter allows multiple power domains to be isolated in the same pad ring while maintaining continuous VDD/VSS for robust ESD protection.
Key Features
- Drive strength – ZOUT = 34 ?
- User programmable on-die termination
- DDR3 – 120 / 60 / 40 / 30 / 20 ?
- DDR4 – 240 / 120 / 80 / 60 / 40 ?
- Operating frequency up to 1200 MHz (2400 MT/sec data rate)
Deliverables
- a. Physical abstract in LEF format (.lef)
- b. Timing models in Synopsys Liberty formats (.lib and .db)
- c. Calibre compatible LVS netlist in CDL format (.cdl)
- d. GDSII stream (.gds)
- e. Behavioral Verilog (.v)
- f. Layout Parasitic Extraction (LPE) SPICE netlist (.spice)
- g. Databook (.pdf)
- h. Library User Guide - ESD Guidelines (.pdf)
Technical Specifications
Foundry, Node
TSMC 28nm
Maturity
Silicon Proven
Availability
Available Now