DDR2/MDDR Combo PHY for Chip load usage ; UMC 65NM SP-RVT with 2.5V device LowK Logic Process
Overview
DDR2/MDDR Combo PHY for Chip load usage ; UMC 65NM SP-RVT with 2.5V device LowK Logic Process
Technical Specifications
Foundry, Node
UMC 65nm
Maturity
Pre-Silicon release
UMC
Pre-Silicon:
65nm
LL
,
65nm
LP
,
65nm
SP
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