DDR Synthesizable Transactor provides a smart way to verify the DDR component of a SOC or a ASIC in Emulator or FPGA platform. The SmartDV's DDR Synthesizable Transactor is fully compliant with standard JESD79F Specification and provides the following features.
DDR Synthesizable Transactor
Overview
Key Features
- Supports 100% of DDR protocol standard JESD79F
- Supports all the DDR commands as per the specs
- Supports all device speeds as per specification
- Supports programmable CAS latency
- Supports programmable burst lengths: 2,4 and 8
- Supports write data mask
- Supports the following devices:
- X4
- X8
- X16
- Supports up to 1 GB device density
- Supports the following burst types:
- Sequential
- Interleave
- Supports burst order
- Supports all mode register programming
- Supports extended mode register programming
- Supports auto refresh & self-refresh modes
- Supports auto precharge option for each burst access
- Supports power down features
- Supports DLL operation
- Checks for following:
- Check-points include power up, initialization and power off rules
- State based rules, active Command rules
- Read/Write command rules etc
- All timing violations
- Bus-accurate timing for min, max and typical values
- Notifies the test bench of significant events such as transactions, warnings, timing and protocol violations
Benefits
- Compatible with testbench writing using SmartDV's VIP
- All UVM sequences/testcases written with VIP can be reused
- Runs in every major emulators environment
- Runs in custom FPGA platforms
Block Diagram
Deliverables
- Synthesizable transactors
- Complete regression suite containing all the DDR testcases
- Examples showing how to connect various components, and usage of Synthesizable Transactor
- Detailed documentation of all DPI, class, task and function's used in verification env
- Documentation contains User's Guide and Release notes